Accepted Papers

  • Design And Implementation Of Power Optimized 64 Bit Floating Point ALU Employing Block Enabling Technique
    B.N.V.Amar Surendra Babu , Y.Syamala and k.Srilakshmi,Gudlavalleru Engineering College,India
    The 64 bit floating point ALU can be used as a coprocessor to a main processor that allowed an embedded system to perform floating point calculations more efficiently and increasing the overall speed of a system. The density and power consumption of processors are limited primarily by power consumption concerns. Hence in this paper implementation of a 64 bit floating point ALU called Math coprocessor with block enabling technique is proposed to decrease the power consumption of the processor and this value is compared with the floating point ALU without block enabling technique. All the modules in floating point unit are realized using verilog HDL. This designed floating point unit is mapped on to vertex5 and vertex 6 low power FPGAs. The simulation is done using Isim simulator and synthesis is carried out using XILINX ISE synthesis tool on the XILINX-14.7 platform. This floating point ALU achieves maximum frequency of 207.168 MHZ with a dynamic power dissipation of 38 mw when operated at a clock frequency of 10MHZ. Finally, it was observed that 12% reduction in dynamic power consumption was achieved by using block enabling technique to the floating point ALU.
  • Design of Balanced Operational Transconductance Amplifier (OTA) using 180nm Technology
    Sharan Hiremath , Twinkle Patel, Kishen Raikar,B. V. Bhoomaraddi College of Engineering and Technology,India
    In this research work, we propose an adaptive genetic algorithm to minimize the sum of weighted tardiness on a single machine, which is a strong NP-hard problem. The algorithm uses the natural permutation representation of a chromosome, an hybrid technique between Multiple Small-Popsize Initialization Strategy (MSPIS) and EDD heuristic dispatching rule to create the initial population, an intelligent technique in crossover step and insertion strategy as a mutation operator to improve individuals of the population during generations. Some results are presented and discussed.
  • A Novel CMOS Dynamic Latch Comparator for Low Power and High Speed
    Shilpi Singh and Dr. Nidhi Goel,Indira Gandhi Technical University For Women, India
    This paper presents a novel dynamic latched comparator that consumes lower power and higher speed than the conventional dynamic latched comparators. This paper also provides a comprehensive review of a variety of comparator designs in terms of power and delay. The comparators and the proposed circuit are designed and simulated their transient responses in Tanner EDA suite using 180 nm CMOS technology and 1V power supply voltage and it demonstrates up to 0.03968 milliwatt power consumption and higher speed with delay of 60.29 picoseconds than the conventional latched comparators
  • High Speed Low Power CMOS Domino OR Gate design in16nm Technology
    P.Koti Lakshmi and Rameshwar Rao, Osmania University, India
    Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 10% variation in supply voltage.
  • Implementation of Vedic Multiplier Using Reversible Gates
    P Koti Lakshmi, B Santhosh Kumar and Rameshwar Rao,Osmania University, India
    With DSP applications evolving continuously, there is continuous need for improved multipliers which are faster and power efficient. Reversible logic is a new and promising field which addresses the problem of power dissipation. It has been shown to consume zero power theoretically. Vedic mathematics techniques have always proven to be fast and efficient for solving various problems. Therefore, in this paper we implement Urdva Tiryakbhayam algorithm using reversible logic thereby addressing two important issues – speed and power consumption of implementation of multipliers. In this work, the design of 4x4 Vedic multiplier is optimized by reducing the number of logic gates, constant inputs, and garbage outputs. This multiplier can find its application in various fields like convolution, filter applications, cryptography, and communication.